A state-of-the-art electronic packaging generally contains many levels of packages and interconnections. The first level package may connect one or more silicon chips on a ceramic substrate carrier. A second level package may interconnect one or more such ceramic substrate carriers on an organic board. In order to achieve high conductivity for power distribution, desirable low electrical inductance for high speed and low noise, proper mechanical properties for acceptable mechanical support, and fatigue characteristics, as well as manufacturability considerations, heretofore ceramic substrate carriers are provided with rigid metal pins which are brazed on the ceramic with a suitable braze material such as a gold-tin alloy. Ceramic substrates with such rigid pins are subsequently plugged into a connector or wave soldered to an array of plated through holes on the organic board. The foregoing described connection system has disadvantages of high cost associated with the braze material, the rigid metal pins, the pin connectors or plated through holes, which holes also limit the number of wiring channels available in the board.
U.S. Pat. Nos. 3,401,126 and 3,429,040 issued to L. F. Miller and assigned to the assignee of the present patent application describes in detail the controlled collapse connection technique of face-down bonding of semiconductor chips to a carrier, i.e. forming a first level package interconnection. In general, what is described in those patents is the formation of a malleable pad of metallic solder on the semiconductor chip contact site and solder joinable sites on the conductors on the chip carrier. The chip carrier joinable sites are surrounded by non-soluable barriers so that when the solder on the carrier sites and the semiconductor device contact sites melt and merge, surface tension holds the semiconductor chip suspended above the carrier.
U.S. Pat. No. 4,545,610 to Mark Lakritz, et al, and assigned to the assignee of the present patent application teaches an improved process over the above described Miller patents for forming elongated solder terminals to connect a plurality of pads on a semiconductor device to a corresponding plurality of pads on a supporting substrate by, forming a means to maintain a predetermined vertical spacing between the semiconductor and the supporting substrate outside the area of the pads, forming and fixing solder extenders to each of the solder vertical pads on the substrate or the device to be joined, positioning the semiconductor device provided with solder mounds on the solder mountable pads on the supporting substrate with the solder mound in registry and with the pads on the substrate with the solder extenders positioned therebetween, the means to maintain vertical spacing located between and in abutting relation to the device and substrate, and heating the resulting assembly to fully melt both the solder mounds and the solder extenders while maintaining a predetermined spacing using stand-offs thus forming a plurality of hour-glass shaped elongated connections for a first level package.
Recently a substantial effort has been directed at extending the first level solder interconnection technique for chips and carriers to the second level interconnections of carriers and supporting higher level packages, such as a circuit board. For example, U.S. Pat. No. 4,664,309, issued on May 12, 1987 to Leslie J. Allen, et al, entitled, "Chip Mounting Device", teaches an interconnection preform placement device having a retaining member with a predefined pattern of holes in which are positioned preforms of joint-forming materials such as solder. The device is placed between parallel patterns of electrically conductive elements on an electronic component and a circuit board to effect the bonding of the conductive elements with the preforms. The preforms maintain their predefined configuration during the bonding and retain their original shape after the connection process. According also to the teaching of the companion U.S. Pat. No. 4,705,205, the joint-forming materials may be a filled solder composition or a support solder having "wool" or wire or mesh, which substantially maintain their physical shape when the solder component of the joint-forming material is molten.
U.S. Pat. No. 4,352,449 issued to Peter M. Hall, et al, entitled "Fabrication of Circuit Packages", teaches a method for mounting a chip carrier on a supporting substrate, wherein solder preforms are applied to contact pads on either the chip carrier or substrate. After contact pads of both the carrier and the substrate are brought into contact with the solder preforms, the bond is formed by heating the final assembly thereby forming the connection by totally melting the solder preforms.
U.S. Pat. No. 4,332,341 issued to Richard H. Minetti entitled "Fabrication of Circuit Packages using Solid Phase Solder Bonding", teaches a method of forming circuit packages including the bonding of the chip carrier into a supporting substrate, wherein solid solder preforms are applied to contact members on the component or substrate or both, the preforms are bonded to the contact members by heating to a temperature below the melting point of solder while applying force to the preforms, thereby forming a connection without melting the preforms.